Methods for Forming Stacked Layers and Devices Formed Thereof

ABSTRACT

A method includes etching a semiconductor substrate to form a trench, with the semiconductor substrate having a sidewall facing the trench, and depositing a first semiconductor layer extending into the trench. The first semiconductor layer includes a first bottom portion at a bottom of the trench, and a first sidewall portion on the sidewall of the semiconductor substrate. The first sidewall portion is removed to reveal the sidewall of the semiconductor substrate. The method further includes depositing a second semiconductor layer extending into the trench, with the second semiconductor layer having a second bottom portion over the first bottom portion, and a second sidewall portion contacting the sidewall of the semiconductor substrate. The second sidewall portion is removed to reveal the sidewall of the semiconductor substrate.

PRIORITY CLAIM AND CROSS-REFERENCE

This application claims the benefit of the U.S. Provisional ApplicationNo. 62/927,547, filed Oct. 29, 2019, and entitled “Methods for ImprovingTransistor with Hybrid Design and Resulting Structures,” whichapplication is hereby incorporated herein by reference.

BACKGROUND

In the formation of integrated circuits, to suit to the design ofdifferent circuits, a plurality of devices may be integrated on a samechip. For example, FinFET transistors, nano-sheet transistors,Gate-All-Around (GAA) transistors, and the like, may be formed on thesame chip. Interface regions are used to separate the different types ofdevices. To improve the overall density of the devices on the chip, theoccupied chip area of the interface regions need to be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIGS. 1 through 17, 18A, 18B-1 and 18B-2 illustrate the cross-sectionalviews of intermediate stages in the formation of stacked layers andtransistors in accordance with some embodiments.

FIGS. 19 through 27 illustrate the cross-sectional views of intermediatestages in the formation of stacked layers in accordance with someembodiments.

FIGS. 28 and 29 illustrate the cross-sectional views of intermediatestages in the formation of stacked layers with upper layers beingincreasing narrower than respective lower layers in accordance with someembodiments.

FIGS. 30 and 31 illustrate the cross-sectional views of intermediatestages in the formation of stacked layers with upper layers beingincreasing wider than respective lower layers in accordance with someembodiments.

FIG. 32 schematically illustrates the different device regions and theinterface regions in accordance with some embodiments.

FIG. 33 schematically illustrates the different device regions forforming different types of devices and the interface regions inaccordance with some embodiments.

FIG. 34 illustrates a process flow for forming stacked layers and aGate-All-Around (GAA) transistor based on the stacked layers inaccordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the invention. Specificexamples of components and arrangements are described below to simplifythe present disclosure. These are, of course, merely examples and arenot intended to be limiting. For example, the formation of a firstfeature over or on a second feature in the description that follows mayinclude embodiments in which the first and second features are formed indirect contact, and may also include embodiments in which additionalfeatures may be formed between the first and second features, such thatthe first and second features may not be in direct contact. In addition,the present disclosure may repeat reference numerals and/or letters inthe various examples. This repetition is for the purpose of simplicityand clarity and does not in itself dictate a relationship between thevarious embodiments and/or configurations discussed.

Further, spatially relative terms, such as “underlying,” “below,”“lower,” “overlying,” “upper” and the like, may be used herein for easeof description to describe one element or feature's relationship toanother element(s) or feature(s) as illustrated in the figures. Thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. The apparatus may be otherwiseoriented (rotated 90 degrees or at other orientations) and the spatiallyrelative descriptors used herein may likewise be interpretedaccordingly.

Stacked layer formed of different materials and the method of formingthe same are provided in accordance with some embodiments. Theintermediate stages in the formation of the stacked layers areillustrated in accordance with some embodiments. Some variations of someembodiments are discussed. Embodiments discussed herein are to provideexamples to enable making or using the subject matter of thisdisclosure, and a person having ordinary skill in the art will readilyunderstand modifications that can be made while remaining withincontemplated scopes of different embodiments. Throughout the variousviews and illustrative embodiments, like reference numbers are used todesignate like elements. Although method embodiments may be discussed asbeing performed in a particular order, other method embodiments may beperformed in any logical order.

In accordance with some embodiments of the present disclosure, theformation of stacked layers include forming a trench, depositing a firstconformal layer formed of a first material, removing the verticalportions of the first conformal layer while leaving the horizontalportions of the first conformal layer un-removed, depositing a secondconformal layer formed of a second material, and removing the verticalportions of the second conformal layer while leaving the horizontalportions of the second conformal layer un-removed. The resulting layersof the first material and the second material include the horizontalportions, but not the vertical portions, in the trench. Since thevertical portions would have occupied chip area, by removing thevertical portions, the interface area of the stacked layers is reduced.It is appreciated that although the subsequent discussed layers 24 and34 are semiconductor layers in some embodiments, these layers may alsobe formed of other materials such as dielectric materials, metallicmaterials, or the like.

FIGS. 1 through 17, 18A, 18B-1 and 18B-2 illustrate the cross-sectionalviews of intermediate stages in the formation of stacked layers and aGate-All-Around (GAA) transistor in accordance with some embodiments ofthe present disclosure. The corresponding processes are also reflectedschematically in the process flow 200 as shown in FIG. 34.

In FIG. 1, substrate 20 is provided. The substrate 20 may be asemiconductor substrate, such as a bulk semiconductor substrate, aSemiconductor-On-Insulator (SOI) substrate, or the like, which may bedoped (e.g., with a p-type or an n-type dopant) or undoped. Thesemiconductor substrate 20 may be a part of wafer 10. Generally, an SOIsubstrate is a layer of a semiconductor material formed on an insulatorlayer. The insulator layer may be, for example, a Buried Oxide (BOX)layer, a silicon oxide layer, or the like. The insulator layer isprovided on a substrate, typically a silicon or glass substrate. Othersubstrates such as a multi-layered or gradient substrate may also beused. In some embodiments, the semiconductor material of semiconductorsubstrate 20 may include silicon; germanium; a compound semiconductorincluding silicon carbide, gallium arsenic, gallium phosphide, indiumphosphide, indium arsenide, and/or indium antimonide; an alloysemiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP,and/or GaInAsP; or combinations thereof.

Referring to FIG. 2, trench 22 is formed. The respective process isillustrated as process 202 in the process flow 200 shown in FIG. 34. Inaccordance with some embodiments, the etching is performed using ananisotropic etching process. For example, when substrate 20 is formed ofor comprise silicon, the etching is performed using a dry etchingmethod, and the etching gas may include C₂F₆, CF₄, SO₂, the mixture ofHBr, Cl₂, and O₂, the mixture of HBr, Cl₂, and O₂, the mixture of HBr,Cl₂, O₂, and CF₂, or the like. The depth D1 of trench 22 is related tothe desirable number of channel layers. In accordance with someembodiments, depth D1 of trench 22 is in the range between about 10 nmand about 200 nm. The resulting trench 22 may have vertical sidewalls asshown in FIG. 2, with tilt angle θ being equal to 90 degrees orsubstantially equal to 90 degrees, for example, in the range betweenabout 89° and about 91°. The tilt angle θ may also be smaller than 89°,for example, in the range between about 85° and about 89°, or greaterthan about 91°, for example, in the range between about 91° and about110°. Tilt angle θ may also be smaller than about 85° or greater thanabout 110°.

FIGS. 3 through 6 illustrate the formation of semiconductor layer 24-1and passivation 28-1 in accordance with some embodiments of the presentdisclosure. Throughout the description, semiconductor layers 24-1through 24-n (FIG. 13) are also collectively and individually referredto as semiconductor layers 24, and passivation layers 28-1 through 28-n(FIG. 13) are also collectively and individually referred to as layers28. FIG. 3 illustrates the deposition of semiconductor layer 24-1. Therespective process is illustrated as process 204 in the process flow 200shown in FIG. 34. Semiconductor layer 24-1 may be formed of a materialdifferent from the material of substrate 20. In accordance with someembodiments, semiconductor layer 24-1 is a semiconductor layer formed ofor comprising SiGe, germanium (free or substantially free from silicon,for example, with Si atomic percentage being lower than about 10percent), SiC, or other materials. In accordance with some embodimentsin which SiGe is used, the germanium atomic percentage may be in therange between about 30 percent and about 60 percent. Higher or loweratomic percentages of germanium are also in the scope of the presentdisclosure. In accordance with some embodiments, the deposition includesan epitaxial growth. In accordance with some embodiments, for example,when GAA transistors are to be formed, semiconductor layers 24-1 through24-n (FIG. 13) may be removed in subsequent processes, and are thusreferred to as sacrificial layers. In accordance with other embodiments,semiconductor layers 24 are not removed, and may be left in the finalstructure.

The deposition may be performed using a conformal deposition method,which may include Atomic Layer Deposition (ALD), Plasma Enhanced AtomicLayer Deposition (PEALD), Chemical Vapor Deposition (CVD), PlasmaEnhanced Chemical Vapor Deposition (PECVD), Physical Vapor Deposition(PVD), or the like. Accordingly, semiconductor layer 24-1 may be aconformal layer, with horizontal thickness T1A and vertical thicknessT1B being equal to each other or substantially equal to each other. Forexample, the horizontal thickness T1A and vertical thickness T1B mayhave a difference smaller than about 20 percent. In accordance with someembodiments, the thicknesses T1 (including T1A and T1B) may be in therange between about 3 nm and about 100 nm, while other thickness rangesare also contemplated.

Next, referring to FIG. 4, passivation process 26 is performed, in whicha process gas is used to passivate a surface layer of a horizontalportion of semiconductor layer 24-1, so that it has an increased etchingselectivity in the subsequent etching process. The respective process isillustrated as process 206 in the process flow 200 shown in FIG. 34. Theprocess gas may include nitrogen (N₂), oxygen (O₂), SO₂, CH₄, CO₂, CO,SiCl₄, or combinations thereof. Other gases such as Ar, He, or the like,may also be added into the process gas. The process gas modifies/treatsthe top surface layer of semiconductor layer 24-1, and the modifiedsurface layer is referred to as passivation layer 28-1. When the processgas comprises oxygen, the surface layer of semiconductor layer 24-1 isoxidized, and passivation layer 28-1 is an oxygen-containing layer. Whenthe process gas comprises nitrogen, the surface layer of semiconductorlayer 24-1 is nitrided, and passivation layer 28-1 is anitrogen-containing layer. Accordingly, passivation layer 28-1 includesthe elements of semiconductor layer 24-1 and additional elements fromthe process gas, and has the property different from the underlyingun-treated portion of semiconductor layer 24-1.

In accordance with some embodiments of the present disclosure, thepassivation is performed through an anisotropic process, so that thesurface layer of the horizontal portions of semiconductor layer 24-1 ispassivated to form passivation layer 28-1, while no passivation layer isformed on the vertical portions of semiconductor layer 24-1. Inaccordance with some embodiments of the present disclosure, thethickness T2 (including T2A and T2B) of the passivation layer is smallerthan about 15 percent of thickness T1 of semiconductor layer 24-1, andratio T2/T1 is smaller than 0.2, and may be in the range between about0.05 and about 0.2. In accordance with alternative embodiments, thetreatment process includes both of a vertical component and a horizontalcomponent, with the vertical component being greater than the horizontalcomponent. As a result, when the passivation layer 28-1 is formed on thehorizontal portions of semiconductor layers 24-1, thinner verticalportions of passivation layers 28-1 are also formed on the verticalportions of semiconductor layer 24-1. The vertical portions of thepassivation layer 28-1 are shown using dashed lines to indicate they mayor may not be formed. The vertical portions of passivation layer 28-1may have thicknesses T2B smaller than about 50 percent, or smaller thanabout 30 percent or 20 percent, of the thicknesses T2A of the horizontalportions.

In accordance with some embodiments of the present disclosure, thepassivation process is performed with a source power in a range betweenabout 10 watts and about 4,000 watts. The bias power may be in the rangebetween about 10 watts and about 4,000 watts, so that adequateanisotropic effect is generated. The pressure of the process gas may bein the range between about 1 mTorr and about 800 mTorr. The flow rate ofthe process gas may be in the range between about 1 sccm and about 5,000sccm.

FIG. 5 illustrates an etching process 30, which may be an isotropicetching process. The respective process is illustrated as process 208 inthe process flow 200 shown in FIG. 34. The etching process is performedusing an etching gas that etches semiconductor layer 24-1, and does notetch passivation layer 28-1. The etching gas may include Cl₂, HBr, CF₄,CHF₃, CH₂F₂, CH₃F, C₄F₆, or combinations thereof. Dilute gases such asAr, He, Ne, or the like, may also be added into the etching gas. In theetching process 30, plasma may be turned on.

In accordance with some embodiments of the present disclosure, theetching process 30 is performed with a source power in a range betweenabout 10 watts and about 4,000 watts. There may not be bias powerapplied (with bias power equal to 0 watts), or the bias power is verylow, for example, lower than about 0.5 watts. The pressure of theetching gas may be in the range between about 1 mTorr and about 800mTorr. The flow rate of the etching gas may be in the range betweenabout 1 sccm and about 5,000 sccm.

In the etching process 30, the etching selectivity, which is the ratioof the etching rate of semiconductor layer 24-1 to the etching rate ofpassivation layer 28-1, is higher than 3, may be higher than about 5,and may be in the range between about 3 and about 50. The horizontalportions of semiconductor layer 24-1 are protected by passivation layer28-1, and are not etched. On the other hand, the vertical portions ofsemiconductor layer 24-1 are etched. When passivation layer 28-1 is alsoformed on the vertical portions of semiconductor layer 24-1, since thevertical portions of passivation layer 28-1 are thinner than thehorizontal portions of passivation layer 28-1, the vertical portionswill be consumed (at a low etching rate) earlier than the horizontalportions, and then the exposed vertical portions of semiconductor layer24-1 are etched. The resulting structure is shown in FIG. 6, in whichthe sidewalls of substrate 20 are exposed. It is appreciated that whenpassivation layer 28-1 does not include vertical portions, passivationlayer 28-1 may still extend to the sidewalls of substrate 20 since thevertical portions of semiconductor layer 24-1 (which are etched) arethin. Alternatively, passivation layer 28-1 may be spaced apart from thesidewalls of substrate 20, and regions 27 do not have passivation layer28-1. In the resulting structure as shown in FIG. 6, semiconductor layer24-1 extends to the sidewalls of substrate 20, while there are novertical portions of semiconductor layer 24-1 remaining. The sidewallsof substrate 20 facing trench 22 are thus revealed again.

In accordance with some embodiments of the present disclosure, in theetching process 30, a byproduct (not shown) may be generated, which maybe accumulated in trench 22, and may be formed on top of sacrificiallayer 28-1. The byproduct is related to the composition of semiconductorlayer 24-1 and the etching gas. For example, the byproduct may includeSiO_(x)Cl_(y) in accordance with some embodiments. The byproduct isremoved, for example, using a chemical solution including H₂SO₄, HNO₃,NH₃, HF, HCl, or combinations thereof. The respective process isillustrated as process 210 in the process flow 200 shown in FIG. 34.Gases such as O₃, H₂, or the like may be added into the chemicalsolution. The solvent of the chemical solution may include water,alcohol, or the like.

FIGS. 7 through 10 illustrate the formation of semiconductor layer 34-1and passivation layer 38-1 in accordance with some embodiments of thepresent disclosure. Throughout the description, semiconductor layers34-1 through 34-n (FIG. 13) are collectively and individually referredto as semiconductor layers 34, and passivation layers 38-1 through 38-n(FIG. 13) are also collectively and individually referred to aspassivation layers 38. FIG. 7 illustrates the deposition ofsemiconductor layer 34-1. The respective process is illustrated asprocess 212 in the process flow 200 shown in FIG. 34. Semiconductorlayer 34-1 is formed of a semiconductor material different from thematerial of semiconductor layer 24-1. In accordance with someembodiments, semiconductor layer 34-1 is formed of or comprises silicon(free from germanium), silicon germanium, or the like. When both ofsemiconductor layers 24-1 and 34-1 comprise silicon germanium, thegermanium percentage of semiconductor layer 34-2 may be lower than (forexample, by around a half) of the germanium percentage of semiconductorlayer 24-1. In accordance with some embodiments in which SiGe is used,the germanium atomic percentage may be lower than about 40 percent,lower than about 20 percent, or lower than about 10 percent.Semiconductor layers 34 may be used as a channel layer of the resultingGAA transistor in accordance with some embodiments, and hence are alsoreferred to as channel semiconductor layers 34.

The deposition of semiconductor layer 34-1 may be performed using aconformal deposition method, which may include ALD, PEALD, PECVD, PVD,or the like. Accordingly, semiconductor layer 34-1 may be a conformallayer, with horizontal thickness T3A and vertical thickness T3B beingequal to each other or substantially equal to each other, for example,with a difference smaller than about 20 percent. In accordance with someembodiments, the thicknesses T3 (including T3A and T3B) may be in therange between about 3 nm and about 100 nm, while other thickness rangesare also contemplated.

Next, referring to FIG. 8, passivation process 36 is performed, in whicha process gas is used to passivate a surface layer of semiconductorlayer 34-1, so that it has an increased etching selectivity in thesubsequent etching process. The respective process is illustrated asprocess 214 in the process flow 200 shown in FIG. 34. The process gasmay also include nitrogen (N₂), oxygen (O₂), SO₂, CH₄, CO₂, CO, SiCl₄,or combinations thereof. Other gases such as Ar, He, or the like, mayalso be added into the process gas. In accordance with some embodimentsof the present disclosure, while both of passivation process 26 (FIG. 4)and passivation process 36 (FIG. 8) may be performed using process gasesselected from the same group of process gases, the processes may be thesame or different from each other. Furthermore, even if the processgases for passivation processes 26 are the same as each other, forexample, all comprising oxygen, the amount of some gases may be tuned toachieve higher etching selectivity in the etching of the respectivevertical portions. For example, when semiconductor layer 24-1 comprisesSiGe, and semiconductor layer 34-1 comprises Si and is free from Ge,passivation process 36-1 may be performed with a higher flow rate of theprocess gas than the passivation process 26 when the process gascomprises O₂. The passivated surface layer of semiconductor layer 34-1is referred to as passivation layer 38-1. When the process gas comprisesoxygen, the surface layer of semiconductor layer 34-1 is oxidized, andpassivation layer 38-1 is an oxygen-containing layer. When the processgas comprises nitrogen, the surface layer of semiconductor layer 34-1 isnitrided, and passivation layer 38-1 is a nitrogen-containing layer.Accordingly, passivation layer 38-1 has the property different from theunderlying un-treated portion of semiconductor layer 34-1.

In accordance with some embodiments of the present disclosure, thepassivation process is an anisotropic process, so that the surface layerof the horizontal portions of semiconductor layer 34-1 is passivated toform passivation layer 38-1, while no passivation layer is formed on thevertical portions of semiconductor layer 34-1. In accordance with someembodiments of the present disclosure, the thickness T4 of thepassivation layer 38-1 is smaller than about 15 percent of thickness T3of semiconductor layer 34-1, and ratio T4/T3 may be in the range betweenabout 0.05 and about 0.2. In accordance with alternative embodiments,the treatment process includes both of a vertical component and ahorizontal component, with the vertical component being greater than thehorizontal component. As a result, when passivation layer 38-1 is formedon the horizontal portion of semiconductor layers 34-1, a thinnervertical portion of the passivation layer 38-1 is formed on the verticalportions of semiconductor layer 34-1. The vertical portions of thepassivation layer 38-1 are shown using dashed lines to indicate they mayor may not be formed. The vertical portions of passivation layer 38-1may have thicknesses T4B smaller than about 50 percent, 20 percent, or10 percent of the thicknesses T4A of the horizontal portions.

In accordance with some embodiments of the present disclosure, thepassivation process 36-1 is performed with a source power in a rangebetween about 10 watts and about 4,000 watts. The bias power may be inthe range between about 10 watts and about 4,000 watts. The pressure ofthe process gas may be in the range between about 1 mTorr and about 800mTorr. The flow rate of the process gas may be in the range betweenabout 1 sccm and about 5,000 sccm.

FIG. 9 illustrates an etching process 40, which may be an isotropicetching process. The respective process is illustrated as process 216 inthe process flow 200 shown in FIG. 34. The etching process is performedusing an etching gas that etches semiconductor layer 34-1, and does notetch passivation layer 38-1. The etching gas may include Cl₂, HBr, CF₄,CHF₃, CH₂F₂, CH₃F, C₄F₆, or combinations thereof. Dilute gases such asAr, He, Ne, or the like, may also be added into the process gas. In theetching process 40, plasma may be turned on.

In accordance with some embodiments of the present disclosure, theetching process 40 is performed with a source power in a range betweenabout 10 watts and about 4,000 watts. There may not be bias powerapplied (bias power equals 0 watts), or the bias power is very low, forexample, lower than about 0.5 watts. The pressure of the etching gas maybe in the range between about 1 mTorr and about 800 mTorr. The flow rateof the etching gas may be in the range between about 1 sccm and about5,000 sccm.

In the etching process 40, the etching selectivity, which is the ratioof the etching rate of semiconductor layer 34-1 to the etching rate ofpassivation layer 38-1, is high, for example, higher than about 5, andmay be in the range between about 3 and about 50. The horizontalportions of semiconductor layer 34-1 are protected by passivation layer38-1, and are not etched. On the other hand, the vertical portions ofsemiconductor layer 34-1 are etched. The resulting structure is shown inFIG. 10, in which the sidewalls of substrate 20 are exposed again. It isappreciated that passivation layer 38-1 may extend to the sidewalls ofsubstrate 20, or may be spaced apart from the sidewalls of substrate 20.Semiconductor layer 34-1 extends to the sidewalls of substrate 20, whilethere are no vertical portions or substantially no vertical portions ofsemiconductor layer 34-1 remaining.

In accordance with some embodiments of the present disclosure, in theetching process 40, a byproduct may be generated, which may includeSiO_(x)Cl_(y) in accordance with some embodiments. The byproduct may beremoved using a chemical solution including H₂SO₄, HNO₃, NH₃, HF, HCl,or combinations thereof. Gases such as O₃, H₂, or the like may be addedinto the chemical solution. The respective process is illustrated asprocess 218 in the process flow 200 shown in FIG. 34. The solvent of thechemical solution may include water, alcohol, or the like.

FIGS. 11 and 12 illustrate the formation of more stacked layers. Therespective process is illustrated as process 220 in the process flow 200shown in FIG. 34. FIG. 11 illustrates the formation of semiconductorlayer 24-2 and passivation layer 28-2. The material and the formationprocesses are similar to the material and the formation processes ofsemiconductor layer 24-1 and passivation layer 28-1, respectively, andare not repeated herein. FIG. 12 illustrates the formation ofsemiconductor layer 34-2 and passivation layer 38-2. The material andthe formation processes are similar to the material and the formationprocesses of semiconductor layer 34-1 and passivation layer 38-1,respectively, and are not repeated herein. There may be, or may not be,more layers such as 24-n, 28-n, 34-n, and 38-n formed, wherein n may be3, 4, 5, or more, for example, up to 10. The resulting structure isshown in FIG. 13, and the resulting stacked layers are referred to asstacked layers 44. In accordance with alternative embodiments of thepresent disclosure, after the process as shown in FIG. 12, no morelayers similar to layers 24-1, 28-1, 34-1, and 38-1 are formed. The toplayer of stacked layers 44 may be a passivation layer 38 of a channel 34or may be the passivation layer 28 of a semiconductor layer 24. Stackedlayer 44 may fully fill trench 22, or may leave a top portion of trench22 unfilled.

FIG. 14 illustrates a planarization process, so that excess materialsoutside of trench 22 are removed. The respective process is illustratedas process 222 in the process flow 200 shown in FIG. 34. Theplanarization may use one of semiconductor layers 24-1, 28-1, 34-1, and38-1 as a CMP stop layer.

In subsequent processes, transistors are formed. In accordance with someembodiments, the formed transistors include a GAA transistor neighboringtwo FinFETs as an example. The formation processes of the transistorsare shown in FIGS. 15 through 17, 18A, 18B-1 and 18B-2.

Referring to FIG. 15, the stacked layers 44 and substrate 20 are etched,forming trenches 46. The respective process is illustrated as process224 in the process flow 200 shown in FIG. 34. The patterned substrate 20and stacked layers 44 form semiconductor strips 48 and the patternedstacked layers 44, respectively. Next, referring to FIG. 16, isolationregions 50 are formed to fill trenches 46. Isolation regions 50 arealternatively referred to as Shallow Trench Isolation (STI) regionshereinafter. The respective process is illustrated as process 226 in theprocess flow 200 shown in FIG. 34. STI regions 50 may include a linerdielectric (not shown), which may be a thermal oxide layer formedthrough the thermal oxidation of a surface layer of substrate 20, and adielectric material over the liner oxide, wherein the dielectricmaterial may be formed using Flowable Chemical Vapor Deposition (FCVD),spin-on coating, or the like. The dielectric material over the linerdielectric may include silicon oxide, silicon nitride, or the like inaccordance with some embodiments.

Referring to FIG. 17, STI regions 50 are recessed, so that the topportions of semiconductor strips 48 protrude higher than the topsurfaces of the remaining portions of STI regions 50 to form protrudingfins 48′. The respective process is illustrated as process 228 in theprocess flow 200 shown in FIG. 34. The etching may be performed using adry etching process, wherein NF₃ and NH₃, for example, are used as theetching gases. During the etching process, plasma may be generated.Argon may also be included. In accordance with alternative embodimentsof the present disclosure, the recessing of STI regions 50 is performedusing a wet etching process. The etching chemical may include HF, forexample. The sidewalls of the stacked layers 44 are thus exposed.

FIGS. 18A, 18B-1, and 18B-2 illustrate the cross-sectional view in theformation of GAA transistor 52 and FinFETs 58. The respective process isillustrated as process 230 in the process flow 200 shown in FIG. 34. Itis appreciated that the cross-sectional view is obtained from thechannels and the gate stacks of GAA transistor 52 and FinFETs 58. Thesource/drain regions of the transistors are in different cross-sections,and are not shown. GAA transistor 52 includes channels 34 (including34-1 through 34-n), gate dielectrics 54 encircling channels 34, and gateelectrode 56. The formation process of GAA transistors 52 and FinFETs 58may include forming dummy gate stacks and gate spacers on the protrudingstructures shown in FIG. 17, forming source/drain regions (not shown),and then forming Contact Etch Stop Layer (CESL) 64 and Inter-LayerDielectric (ILD) 66. One or a plurality of etching processes are thenperformed to remove the dummy gate stacks, sacrificial semiconductorlayers 24, passivation layers 28 (including 28-1 through 28-n), andpassivation layers 38 (including 38-1 through 38-n). Channelsemiconductor layers 34-1 through 34-n are left unremoved. Gatedielectrics 54 and a replacement gate electrode 56 (which may be metalgate electrode) are then formed. FinFETs 58 are also formed. It isappreciated that although the illustrated example embodiment show thatGAA transistors 52 and FinFETs 58 share a same replacement gateelectrode 54, as shown in FIG. 18A, in other embodiments, they may notshare the replacement gate electrode 54, as is shown in FIGS. 18B-1 and18B-2. FIG. 18B-1 illustrates that the cutting between the gate stacksof the GAA transistors 52 and FinFETs 58 is performed before theformation of the replacement gates. Accordingly, gate dielectrics 54 andgate electrodes 56 (including, for example, work function layer 56-1 andother metal layers 56-2) have sidewall portions. In accordance withthese embodiments, the cuts may be performed on the dummy gateelectrodes (not shown). FIG. 18-2 illustrates the cutting between thegate stacks of the GAA transistors 52 and FinFETs 58 is performeddirectly on the replacement gates. Accordingly, gate dielectrics 54 andgate electrodes 56 (including, for example, work function layer 56-1 andother metal layers 56-2) do not have sidewall portions.

In accordance with some embodiments, FinFETs 58 and GAA transistor 52are closely located. The sizes of the interface area between GAAtransistor 52 and its neighboring FinFETs 58 are affected by the stackedlayers 44. For example, if stacked layers 44 are formed as beingconformal layers extending into trench 22 (FIG. 2), each of the stackedlayers 44 will have sidewall portions, and all of the sidewall portionswill occupy chip area. This would significantly increase the interfacearea between GAA transistors and neighboring transistors. By selectivelyremoving the sidewall portions of the stacked layers from the trenc theinterface area is reduced. The interface region between GAA transistor52 and its neighboring FinFETs 58 is reduced, and the density of devicesmay be reduced.

FIGS. 19 through 27 illustrate the cross-sectional views of intermediatestages in the formation of stacked layers 44′ in accordance with someembodiments of the present disclosure. These embodiments are similar tothe embodiments shown in FIGS. 1 through 17, 18A, 18B-1, and 18B-2,except that instead of forming passivation layers prior to etching inorder to protect the horizontal portions of the stacked layers, theetching is started without the passivation layer, and the byproduct ofthe etching are used. Accordingly, the two-step etching processes forremove the vertical portions of the stacked layers are replaced withone-step etching processes. Unless specified otherwise, the materialsand the formation processes of the components in these embodiments areessentially the same as the like components, which are denoted by likereference numerals in the preceding embodiments shown in FIGS. 1 through18. The details regarding the formation processes and the materials ofthe components shown in FIGS. 19 through 27 may thus be found in thediscussion of the preceding embodiments.

The initial processes of these embodiments are essentially the same asshown in FIGS. 1 through 3, and the resulting structure is shown in FIG.19, in which semiconductor layer 24-1 is formed. Next, as shown in FIG.20, an isotropic etching process 70 is performed. The process gasincludes both of an etching gas(es) and a passivation gas(es). Theetching gas may include Cl₂, HBr, CF₄, CHF₃, CH₂F₂, CH₃F, C₄F₆, orcombinations thereof. The passivation gas may also include nitrogen(N₂), oxygen (O₂), SO₂, CH₄, CO₂, CO, SiCl₄, or combinations thereof.Other gases such as Ar, He, Ne, or the like, may also be added into theprocess gas. In accordance with some embodiments of the presentdisclosure, the etching process is performed with a source power in arange between about 10 watts and about 4,000 watts. There may not bebias power applied (with the bias power being equal 0 watts), or thebias power is very low, for example, lower than about 0.5 watts. Thepressure of the process gas may be in the range between about 1 mTorrand about 800 mTorr. The flow rate of the process gas may be in therange between about 1 sccm and about 5,000 sccm.

Referring to FIG. 20, in the etching process 70, byproduct layer 68 isformed, and is deposited on the horizontal surfaces of semiconductorlayer 24-1. On the vertical portions of semiconductor layer 24-1, thebyproduct layer 68 has less chance to stay due to the conductanceeffect, and will be pumped out of the respective etching chamber. Thebyproduct layer 68 may include SiOBrCl, for example. The byproduct layer68 protects the horizontal portions of semiconductor layer 24-1, andhence the vertical portions of semiconductor layer 24-1 can be removed,resulting in the structure shown in FIG. 21. Process gases and etchingconditions may be adjusted to increase the generation of the byproductlayer 68 in order to provide adequate protection of the horizontalportions of semiconductor layer 24-1. For example, the flow rate of theoxygen-containing gas(es) in the passivation gas may be increased, forexample, to about 1 sccm and about 1000 sccm, so that byproduct layer 68is generated faster.

Referring to FIG. 21, after the vertical portions of the semiconductorlayer 24-1 are removed, the byproduct layer 68 may be removed in anisotropic etching process 72. The etchant may include H₂SO₄, HNO₃, NH₃,HF, HCl, or combinations thereof. Gases such as O₃, H₂, or the like maybe added into the chemical solution. The solvent of the chemicalsolution may include water, alcohol, or the like. The resultingstructure is shown in FIG. 22.

FIG. 23 illustrates the deposition of semiconductor layer 34-1, whichmay be a conformal layer. Next, as shown in FIG. 24, an isotropicetching process 74 is performed to etch the vertical portions ofsemiconductor layer 34-1, while the horizontal portions of thesemiconductor layer 34-1 are etched less and will have majorityremaining. The etching process may be performed using a process gascomprising both of an etching gas(es) and a passivation gas, wherein theexample gases and process conditions may be similar to the process 70shown in FIG. 20. Byproduct layer 76 is thus formed on the horizontalportions of semiconductor layer 34-1 so that the vertical portions ofsemiconductor layer 34-1 are selectively removed. FIG. 25 illustratesthe etching process 78 for removing byproduct layer 76.

In subsequent processes, more semiconductor layers 24 (including 24-2through 24-n) and semiconductor layers 34 (including 34-2 through 34-n)may be formed using the similar processes as shown in FIGS. 19 through25. Stacked layers 44′, which include semiconductor layers 34 andsemiconductor layer 24, are thus formed. A planarization process is thenperformed, resulting in the structure shown in FIG. 27. The subsequentprocesses are similar to the processes shown in FIGS. 15 through 17,18A, 18B-1, and 18B-2, which are not repeated herein.

By adopting the embodiments of the present disclosure, stacked layers 44or 44′ may have different types of edge profiles other than the edgeprofiles shown in FIGS. 18 and 27. For example, FIGS. 28 and 29illustrate the formation of stacked layers 44 with sharp or obtuse tiltangles θ. FIG. 28 illustrates the etching of substrate 20 to form trench22 with sharp tilt angles θ. Next, the deposition processes as shown inFIGS. 3 through 14 are performed to form stacked layers 44, as shown inFIG. 29. In accordance with some embodiments, as aforementioned inpreceding paragraphs, the tilt angle θ may also be smaller than 89°, forexample, in the range between about 85° and about 89°. Tilt angle θ mayalso be smaller than about 85°.

FIG. 30 illustrates the etching of substrate 20 to form trench 22 havingobtuse tilt angles θ. Next, the deposition processes as shown in FIGS. 3through 14 are performed to form stacked layers 44, as shown in FIG. 31.In accordance with some embodiments, as aforementioned in precedingparagraphs, the tilt angle θ may be greater than about 91°, for example,in the range between about 91° and about 110°. Tilt angle θ may also begreater than about 110°. It is appreciated that the stacked layers 44 inFIG. 14 and the stacked layer 44′ as shown in FIG. 27 may also have thetilt angle θ as shown in FIG. 29 or 31.

FIG. 32 illustrates a top view of some regions including GAA region110G, FinFET regions 100F, and interface regions 100I. GAA region 110Gis used for forming a GAA transistor (for example, similar to GAAtransistor 52 in FIGS. 18A, 18B-1 and 18B-2). The top view in FIG. 32may reflect the top view of the structure shown in FIGS. 18A, 18B-1 and18B-2. FinFET regions 110F are used for having FinFETs (for example,FinFETs 58 in FIGS. 18A, 18B-1 and 18B-2). Interface regions 100I mayinclude the slant-edge regions 100I in FIG. 29 or 31 and the regions forproviding process margin. As can be realized, if the stacked layers areconformal layers having vertical portions, the vertical portions arealso in the interface regions. Accordingly, by forming stacked layers intrenches with the vertical portions removed, the interface regions 100Imay be minimized.

FIG. 33 illustrates some portions of a wafer 10, which may include aplurality of regions. For example, there may be a plurality of (such as2, 3, . . . up to 10 or more) single-channel transistor regions 100F,with the transistors therein having designs different from each other.There may be a plurality of (such as 2, 3, or more) multi-channeltransistor regions (such as the GAAs with a plurality of channellayers), with the transistors therein having designs different from eachother. For example, FIG. 33 illustrates that the channel layers in GAAregions 100GA and 100GB have their channel semiconductor layers 34A and34B formed of different materials. The single-channel transistors mayhave different channel materials, different channel widths, or the like.Interface regions 100I separate the multiple device regions. By adoptingthe embodiments of the present disclosure, the interface regions betweenthe device regions are smaller, and the density of devices may beincreased.

It is appreciated that although in the example embodiments,semiconductor layers 24 and 34 are both formed of semiconductormaterials, the embodiments may be applied on the formation of stackedlayers formed of any other types of materials. For example, each oflayers 24 and 34 may be formed of a material selected from semiconductormaterials, dielectric material, metals or metal alloys, non-metalconductive materials, or the like. By adopting the embodiments of thepresent disclosure, stacked layers with horizontal portions but do nothave vertical portions may be formed in trenches.

The embodiments of the present disclosure have some advantageousfeatures. In the formation of stacked layers, the vertical portions ofthe stacked layers are selectively removed. By removing the verticalportions of the stacked layers, the chip area occupied by the stackedlayers is reduced, and the interface regions between different types ofdevices are smaller. The resulting devices may have a high density.

In accordance with some embodiments of the present disclosure, a methodincludes etching a semiconductor substrate to form a trench, wherein thesemiconductor substrate comprises a sidewall facing the trench;depositing a first semiconductor layer extending into the trench,wherein the first semiconductor layer comprises a first bottom portionat a bottom of the trench, and a first sidewall portion on the sidewallof the semiconductor substrate; removing the first sidewall portion toreveal the sidewall of the semiconductor substrate; depositing a secondsemiconductor layer extending into the trench, wherein the secondsemiconductor layer comprises a second bottom portion over the firstbottom portion, and a second sidewall portion contacting the sidewall ofthe semiconductor substrate; and removing the second sidewall portion toreveal the sidewall of the semiconductor substrate. In an embodiment,the first semiconductor layer and the second semiconductor layer areformed of different semiconductor materials. In an embodiment, theremoving the first sidewall portion comprises performing a passivationprocess on the first semiconductor layer; and after the passivationprocess, performing an isotropic etching process on the firstsemiconductor layer. In an embodiment, the passivation process comprisesan anisotropic passivation process on the first semiconductor layer. Inan embodiment, the passivation process results in a top surface layer ofthe first semiconductor layer to be converted into a passivation layer,and in the isotropic etching process, the passivation layer protects thefirst bottom portion from being removed. In an embodiment, the removingthe first sidewall portion comprises performing an isotropic etchingprocess on the first semiconductor layer using a process gas, whereinwhen the removing is started, both of the first bottom portion and thefirst sidewall portion are exposed to the process gas. In an embodiment,the process gas comprises an etching gas configured to etch the firstsemiconductor layer; and a byproduct-generating gas configured togenerate a byproduct. In an embodiment, in the isotropic etchingprocess, a byproduct layer is generated on a top surface of the firstbottom portion to protect the first bottom portion from being etched. Inan embodiment, the method further includes patterning the firstsemiconductor layer and the second semiconductor layer to form apatterned layer-stack; removing the first semiconductor layer; andforming a gate dielectric comprising portions contacting both of a topsurface and a bottom surface of the second semiconductor layer.

In accordance with some embodiments of the present disclosure, a methodincludes forming a trench extending into a substrate; depositing a firstlayer comprising portions extending into the trench, wherein the firstlayer comprises first horizontal portions; and a first vertical portionin the trench and contacting a sidewall of the substrate; performing afirst anisotropic treatment process to form a passivation layer on thefirst horizontal portions of the first layer; and performing a firstisotropic etching process to remove the first vertical portion of thefirst layer. In an embodiment, the depositing the first layer comprisesan epitaxy process to grow a material selected from the group consistingof silicon, germanium, and combinations thereof. In an embodiment, thefirst anisotropic treatment process comprises a plasma treatment processusing a process gas selected from the group consisting of nitrogen (N₂),oxygen (O₂), SO₂, CH₄, CO₂, CO, SiCl₄, and combinations thereof. In anembodiment, the method further includes depositing a second layer overand contacting the passivation layer. In an embodiment, the second layercomprises additional portions extending into the trench, and wherein thesecond layer comprises second horizontal portions; and a second verticalportion in the trench and contacting the sidewall of the substrate.

In accordance with some embodiments of the present disclosure, a methodincludes etching a semiconductor substrate to form a trench; growing afirst semiconductor layer comprising a first bottom portion at a bottomof the trench; and a first sidewall portion in the trench and contactinga sidewall of the semiconductor substrate; forming a first passivationlayer at the bottom of the trench and over the first bottom portion ofthe first semiconductor layer; and etching the first sidewall portion ofthe first semiconductor layer, with the first bottom portion being leftafter the first sidewall portion is etched. In an embodiment, when thefirst passivation layer is formed at the bottom of the trench, the firstpassivation layer is not formed on the first sidewall portion of thefirst semiconductor layer. In an embodiment, when the first passivationlayer is formed at the bottom of the trench, an extension portion of thefirst passivation layer is formed on the first sidewall portion of thefirst semiconductor layer, and the extension portion is thinner than thefirst passivation layer at the bottom of the trench. In an embodiment,the method further includes growing a second semiconductor layerincluding a second bottom portion at the bottom of the trench and overthe first passivation layer; and a second sidewall portion in thetrench; forming a second passivation layer at the bottom of the trenchand over the second bottom portion of the second semiconductor layer;and etching the second sidewall portion of the second semiconductorlayer. In an embodiment, the method further includes removing the firstbottom portion of the first semiconductor layer. In an embodiment, themethod further includes removing the first passivation layer and thesecond passivation layer.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A method comprising: etching a semiconductorsubstrate to form a trench, wherein the semiconductor substratecomprises a sidewall facing the trench; depositing a first semiconductorlayer extending into the trench, wherein the first semiconductor layercomprises a first bottom portion at a bottom of the trench, and a firstsidewall portion on the sidewall of the semiconductor substrate;removing the first sidewall portion to reveal the sidewall of thesemiconductor substrate; depositing a second semiconductor layerextending into the trench, wherein the second semiconductor layercomprises a second bottom portion over the first bottom portion, and asecond sidewall portion contacting the sidewall of the semiconductorsubstrate; and removing the second sidewall portion to reveal thesidewall of the semiconductor substrate.
 2. The method of claim 1,wherein the first semiconductor layer and the second semiconductor layerare formed of different semiconductor materials.
 3. The method of claim1, wherein the removing the first sidewall portion comprises: performinga passivation process on the first semiconductor layer; and after thepassivation process, performing an isotropic etching process on thefirst semiconductor layer.
 4. The method of claim 3, wherein thepassivation process comprises an anisotropic passivation process on thefirst semiconductor layer.
 5. The method of claim 3, wherein thepassivation process results in a top surface layer of the firstsemiconductor layer to be converted into a passivation layer, and in theisotropic etching process, the passivation layer protects the firstbottom portion from being removed.
 6. The method of claim 1, wherein theremoving the first sidewall portion comprises performing an isotropicetching process on the first semiconductor layer using a process gas,wherein when the removing is started, both of the first bottom portionand the first sidewall portion are exposed to the process gas.
 7. Themethod of claim 6, wherein the process gas comprises: an etching gasconfigured to etch the first semiconductor layer; and abyproduct-generating gas configured to generate a byproduct.
 8. Themethod of claim 6, wherein in the isotropic etching process, a byproductlayer is generated on a top surface of the first bottom portion toprotect the first bottom portion from being etched.
 9. The method ofclaim 1 further comprising: patterning the first semiconductor layer andthe second semiconductor layer to form a patterned layer-stack; removingthe first semiconductor layer; and forming a gate dielectric comprisingportions contacting both of a top surface and a bottom surface of thesecond semiconductor layer.
 10. A method comprising: forming a trenchextending into a substrate; depositing a first layer comprising portionsextending into the trench, wherein the first layer comprises: firsthorizontal portions; and a first vertical portion in the trench andcontacting a sidewall of the substrate; performing a first anisotropictreatment process to form a passivation layer on the first horizontalportions of the first layer; and performing a first isotropic etchingprocess to remove the first vertical portion of the first layer.
 11. Themethod of claim 10, wherein the depositing the first layer comprises anepitaxy process to grow a material selected from the group consisting ofsilicon, germanium, and combinations thereof.
 12. The method of claim10, wherein the first anisotropic treatment process comprises a plasmatreatment process using a process gas selected from the group consistingof nitrogen (N₂), oxygen (O₂), SO₂, CH₄, CO₂, CO, SiCl₄, andcombinations thereof.
 13. The method of claim 10 further comprising:depositing a second layer over and contacting the passivation layer. 14.The method of claim 13, wherein the second layer comprises additionalportions extending into the trench, and wherein the second layercomprises: second horizontal portions; and a second vertical portion inthe trench and contacting the sidewall of the substrate.
 15. A methodcomprising: etching a semiconductor substrate to form a trench; growinga first semiconductor layer comprising: a first bottom portion at abottom of the trench; and a first sidewall portion in the trench andcontacting a sidewall of the semiconductor substrate; forming a firstpassivation layer at the bottom of the trench and over the first bottomportion of the first semiconductor layer; and etching the first sidewallportion of the first semiconductor layer, with the first bottom portionbeing left after the first sidewall portion is etched.
 16. The method ofclaim 15, wherein when the first passivation layer is formed at thebottom of the trench, the first passivation layer is not formed on thefirst sidewall portion of the first semiconductor layer.
 17. The methodof claim 15, wherein when the first passivation layer is formed at thebottom of the trench, an extension portion of the first passivationlayer is formed on the first sidewall portion of the first semiconductorlayer, and the extension portion is thinner than the first passivationlayer at the bottom of the trench.
 18. The method of claim 15 furthercomprising: growing a second semiconductor layer comprising: a secondbottom portion at the bottom of the trench and over the firstpassivation layer; and a second sidewall portion in the trench; forminga second passivation layer at the bottom of the trench and over thesecond bottom portion of the second semiconductor layer; and etching thesecond sidewall portion of the second semiconductor layer.
 19. Themethod of claim 18 further comprising removing the first bottom portionof the first semiconductor layer.
 20. The method of claim 19 furthercomprising removing the first passivation layer and the secondpassivation layer.